cs350/kern/arch/mips/locore/cache-mips161.S

/*
 * Copyright (c) 2001, 2009
 *	The President and Fellows of Harvard College.
 *
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 * modification, are permitted provided that the following conditions
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 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE
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 */

#include <kern/mips/regdefs.h>

   /*
    * Cache flushing code for the System/161 MIPS variant, which
    * (for now at least) has magically coherent caches. Almost all
    * real MIPS processors require explicit cache control of one
    * form or another; it can be quite a nuisance. (It is particularly
    * nasty on the MIPS-1, that is, r2000/r3000.)
    */

   .text
   .set noreorder

   .globl mips_flushicache
   .type mips_flushicache,@function
   .ent mips_flushicache
mips_flushicache:
   j ra
   nop
   .end mips_flushicache